A pin electronics of a semiconductor test device includes a driver applying a signal to a device under test. The driver performs an output operation of a signal in synchronization with a clock signal to be inputted. Since a time length of a signal path at each input/output pin in the device under test varies, timing for outputting a signal from each driver is shifted from expected timing in an initial state. Because of this, timing calibration is preformed before performing various tests to the device under test (for example, see Patent Document 1).
FIG. 3 is a diagram showing a configuration of a conventional semiconductor test device capable of modifying an output level (amplitude) of a driver. FIG. 4 is a flowchart showing an operation procedure of timing calibration performed with the configuration shown in FIG. 3. Initially, calibration is performed in an arbitrary fixed condition (time length data showing rise timing of a clock signal in the fixed condition is stored in a clock timing register 110, and level data specifying the output level of the driver is stored in a level register 102) (step 200). Various conventionally known methods can be used as a specific method for the calibration. For example, a case can be considered such as input timing of a strobe signal regulates rise timing of a clock signal outputted from a driver 100 by using a known reference comparator. Thus, timing calibration up to an output terminal A of the test device is performed when an output level of the clock signal outputted from the driver 100 has a certain value. Time-length data as a result of the calibration is stored in a calibration register 112.
Next, a device test condition to be actually performed is set (step 201). Level data of a clock signal to be inputted to a device under test is stored in the level register 102 at setting of the test condition. When the level data of the clock signal is modified, the timing calibration is required each time, and then, calibration is performed based on the test condition (step 202). Time length data newly obtained by the calibration is stored in the calibration register 112.
FIGS. 5 and 6 are explanatory diagrams of the calibration operation according to a level modification. When two kinds of clock signals with a high level and a low level are considered, time necessary for a high-level clock signal to rise is Ta and time necessary for a low-level clock signal to rise is Tb, as shown in FIG. 5. If a high/low detection of the clock signal is performed with 50% of a voltage of an amplitude in the clock signal as a threshold value, the high-level clock signal changes from low level to high level at a time Ty (=Ta/2) after starting rising, while the low-level clock signal changes from low level to high level at a time Tx (=Tb/2) after starting rising. Since Ty>Tx, timing from low level to high level varies only by changing an amplitude level of the clock signal so that timing calibration for regulating this variation is required. Specifically, as shown in FIG. 6, timing that amplitudes of the respective clock signals become 50% is made identical by delaying timing for starting rising of the low-level clock signal (or timing for starting rising of the high-level clock signal may be contrarily increased). After the calibration corresponding to an actual test condition is performed in this manner, a function test or the like (device measurement) to a device under test is performed (step 203). In the case where the device measurement is performed N times with the test condition changed, the operations in steps 201 to 203 are repeated N times. Patent Document 1: Japanese Patent Laid-Open No. 2004-20408 (pp. 2-4, FIGS. 17 to 22)